I am currently a Senior Research Scientist at Georgia Tech working in the School of Computer Science in the College of Computing since 2015. Previously, I have worked as as a research scientist in the School of Computational Science and Engineering (CSE) from 2013 to 2015. This work focused on advanced user support and benchmarking for the Keeneland project and investigating architecture-related research topics for Dr. Jeff Vetter’s Future Technologies Group at Oak Ridge National Lab.
With a background in computer architecture, my main research interests are focused on the intersection of high-performance computing and novel accelerators including GPUs, Xeon Phi, FPGAs, and Arm SVE processors. I am currently working on a collaborative research program for near-memory computing with High Bandwidth Memory (HBM) for processors and GPUs, SuperSTARLU, which is funded by the NSF. I am co-director of Georgia Tech’s Center for High Performance Computing, and I am also the director of a novel architecture testbed, the CRNCH Rogues Gallery, that aims to simplify and democratize access to novel post-Moore accelerators in the neuromorphic, reversible, and novel networking spaces.
I defended my PhD in August 2013 in the area of computer architecture working under Dr. Sudhakar Yalamanchili. More information on this networks- and memory-related research can be found under the publications tab.
Helen Xu comes to Georgia Tech from Lawrence Berkeley National Laboratory where she was the 2022 Grace Hopper Postdoctoral Scholar. She completed her Ph.D. at MIT in 2022 with Professor Charles E. Leiserson. Her main research interests are in parallel and cache-friendly algorithms and data structures. Her work has previously been supported by a National Physical Sciences Consortium fellowship and a Chateaubriand fellowship. She has interned at Microsoft Research, NVIDIA Research, and Sandia National Laboratories.
Parallel ComputingCache-Efficient AlgorithmsPerformance Engineering
Richard (Rich) Vuduc is an Associate Professor at the Georgia Institute of Technology (“Georgia Tech”), in the School of Computational Science and Engineering, a department devoted to the study of computer-based modeling and simulation of natural and engineered systems. His research lab, The HPC Garage (@hpcgarage), is interested in high-performance computing, with an emphasis on algorithms, performance analysis, and performance engineering. He is a recipient of a DARPA Computer Science Study Groupgrant; an NSF CAREER award; a collaborative Gordon Bell Prize in 2010; Lockheed-Martin Aeronautics Company Dean’s Award for Teaching Excellence (2013); and Best Paper Awards at the SIAM Conference on Data Mining (SDM, 2012) and the IEEE Parallel and Distributed Processing Symposium (IPDPS, 2015), among others. He has also served as his department’s Associate Chair and Director of its graduate programs. External to Georgia Tech, he currently serves as Chair of the SIAM Activity Group on Supercomputing (2018-2020); co-chaired the Technical Papers Program of the “Supercomputing” (SC) Conference in 2016; and serves as an associate editor of both the International Journal of High-Performance Computing Applications and IEEE Transactions on Parallel and Distributed Systems. He received his Ph.D. in Computer Science from the University of California, Berkeley, and was a postdoctoral scholar in the Center for Advanced Scientific Computing the Lawrence Livermore National Laboratory.
Shyh-Chiang Shen received his Ph.D. degree in electrical engineering at the University of Illinois at Urbana-Champaign (UIUC) in 2001. He was a key contributor of high-cycle low-voltage radio-frequency (RF) microelectromechanical system (MEMS) switches and GaAs metal-semiconductor field effect transistors (MESFETs) millimeter-wave integrated circuits (MMICs) during his tenure at UIUC. At Xindium Technologies (2000-2004), he developed a proprietary commercial-grade InP single-heterojunction bipolar transistor (SHBT) technology that led to the first demonstration of monolithically integrated 40Gb/s PIN+TIA differential-output optical receivers.
Shen joined the Georgia Institute of Technology in 2005 as an Assistant Professor and was promoted a Full Professor in 2018. His research has yielded 8 awarded U.S. patents, 5 book chapters, 170+ publications in refereed journals and conferences, and many invited seminar talks to date. He is also an editor of a book entitled Nitride Semiconductor LEDs (2nd Ed., October 2017.) His current research is focused on wide bandgap semiconductor (WBG) microelectronics and optoelectronic devices with emphasis on physical device study, fabrication processing technique development, and device characterizations.
High sensitivity, III-nitride-based UV photodetectorsAdvanced III-nitride coherent light emittersIII-nitride transistor technologies (unipolar and bipolar transistors)WBG high power electronicsCompound-semiconductor Integrated circuit technologiesSustainable, “green” technologies
Vivek Sarkar is Chair of the School of Computer Science at Georgia Tech, where he is also the Stephen Fleming Chair for Telecommunications in the College of Computing. He conducts research in multiple aspects of parallel computing software including programming languages, compilers, runtime systems, and debuggers for parallel, heterogeneous and high-performance computer systems. Prof. Sarkar currently leads the Habanero Extreme Scale Software Research Laboratory at Georgia Tech, and is co-director of the Center for Research into Novel Computing Hierarchies (CRNCH). He is also the instructor for a 3-course online specialization on Parallel, Concurrent, and Distributed Programming hosted on Coursera.
Prior to joining Georgia Tech in 2017, Prof. Sarkar was the E.D. Butcher Chair in Engineering at Rice University, where he created the Habanero Lab, served as Chair of the Department of Computer Science during 2013–2016, and created a sophomore-level undergraduate course on Fundamentals of Parallel Programming. Before joining Rice in 2007, Sarkar was Senior Manager of Programming Technologies at IBM Research. His research projects at IBM included the X10 programming language, the Jikes Research Virtual Machine for the Java language, the ASTI optimizer used in IBM’s XL Fortran product compilers, and the PTRAN automatic parallelization system. Sarkar became a member of the IBM Academy of Technology in 1995, and was inducted as an ACM Fellow in 2008. He has been serving as a member of the US Department of Energy’s Advanced Scientific Computing Advisory Committee (ASCAC) since 2009, and on CRA’s Board of Directors since 2015.
I am a professor of Physics at Georgia Tech. I use advanced computational techniques, hybrid computer architectures, and innovative algorithms to answer fundamental questions related to the observational appearance of black holes, the properties of magnetohydrodynamic turbulence, and the interaction of matter with radiation in extreme conditions.
I am a founding member of the Event Horizon Telescope, the international mm-VLBI experiment that has taken the first picture of a black hole with the horizon-scale resolution, and served for three years (2016-2019) as the Project Scientist of the collaboration.
Before moving to Georgia Tech in 2022, I was a professor of Physics and Astronomy at the University of Arizona and the Chair of the Theoretical Astrophysics Program there.
Black Hole Images General Relativity
Dr. Haesun Park is a Regents' Professor and Chair in the School of Computational Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia, U.S.A. She was elected as a SIAM Fellow in 2013 and IEEE Fellow in 2016 for her outstanding contributions in numerical computing, data analysis, and visual analytics. She was the Executive Director of Center for Data Analytics 2013-2015 and was the director of the NSF/DHS FODAVA-Lead (Foundations of Data and Visual Analytics) Center 2008-2014. She has published extensively in the areas of numerical computing, large-scale data analysis, visual analytics, text mining, and parallel computing. She was the conference co-chair for SIAM International Conference on Data Mining in 2008 and 2009 and an editorial board member of the leading journals in computational science and engineering such as IEEE Transactions on Pattern Analysis and Machine Intelligence, SIAM Journal on Matrix Analysis and Applications, and SIAM Journal on Scientific Computing. She was the plenary keynote speaker at major international conferences including SIAM Conference on Applied Linear Algebra in 1997 and 2015, and SIAM International Conference on Data Mining in 2011. Before joining Georgia Tech, she was a professor in Department of Computer Science and Engineering, University of Minnesota, Twin Cities 1987- 2005 and a program director in the Computing and Communication Foundations Division at the National Science Foundation, Arlington, VA, U.S.A., 2003 - 2005. She received a Ph.D. and an M.S. in Computer Science from Cornell University, Ithaca, NY in 1987 and 1985, respectively, and a B.S. in Mathematics from Seoul National University, Seoul, Korea in 1981 with the Presidential Medal for the top graduate.
Bioinformatics; Computer Vision
Saibal Mukhopadhyay received the bachelor of engineering degree in electronics and telecommunication engineering from Jadavpur University, Calcutta, India in 2000 and the Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in August 2006. He joined the faculty of the Georgia Institute of Technology in September 2007. Mukhopadhyay worked at IBM T. J. Watson Research Center, Yorktown Heights, N.Y. as research staff member from August 2006 to September 2007 and as an intern in summers of 2003, 2004, and 2005. At IBM, his research primarily focused on technology-circuit co-design methodologies for low-power and variation tolerant static random access memory (SRAM) in sub-65nm silicon technologies. Mukhopadhyay has (co)-authored over 90 papers in reputed conferences and journals and filed seven United States patents
Low-power, variation tolerant, and reliable VLSI systemsDevice/circuit level modeling/estimation of power, yield, and reliabilityTechnology-circuit co-design methodologiesSelf-adaptive systems with on-chip sensing and repair techniqueMemory design for VLSI applicationsUltra-low power and fault-tolerant nanoelectronics: technology, circuit, and computing platforms