I am currently a Senior Research Scientist at Georgia Tech working in the School of Computer Science in the College of Computing since 2015. Previously, I have worked as as a research scientist in the School of Computational Science and Engineering (CSE) from 2013 to 2015. This work focused on advanced user support and benchmarking for the Keeneland project and investigating architecture-related research topics for Dr. Jeff Vetter’s Future Technologies Group at Oak Ridge National Lab.

With a background in computer architecture, my main research interests are focused on the intersection of high-performance computing and novel accelerators including GPUs, Xeon Phi, FPGAs, and Arm SVE processors. I am currently working on a collaborative research program for near-memory computing with High Bandwidth Memory (HBM) for processors and GPUs, SuperSTARLU, which is funded by the NSF. I am co-director of Georgia Tech’s Center for High Performance Computing, and I am also the director of a novel architecture testbed, the CRNCH Rogues Gallery, that aims to simplify and democratize access to novel post-Moore accelerators in the neuromorphic, reversible, and novel networking spaces.

I defended my PhD in August 2013 in the area of computer architecture working under Dr. Sudhakar Yalamanchili. More information on this networks- and memory-related research can be found under the publications tab.